Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09960399
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Filing Dt:
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09/24/2001
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Publication #:
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Pub Dt:
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12/26/2002
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Inventors:
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Hiroshi Hashimoto, Koji Takahashi
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Title:
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A SEMICONDUCTOR INTEGRATED CIRCUIT AND FABRICATION PROCESS HAVING COMPENSATED STRUCTURES TO REDUCE MANUFACTURING DEFECTS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1-1, KAMIKODANAKA 4-CHOME, NAKAHARA-KU |
| KAWASAKI-SHI, KANAGAWA, 211-8588, JAPAN |
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| ARMSTRONG, WESTERMAN, HATTORI ET AL |
| MEL R. QUINTOS |
| 1725 K ST., N.W., SUITE 1000 |
| WASHINGTON, D.C. 20006 |
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Assignment:
2
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CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF CONVEYING PARTY THAT WAS PREVIOUSLY RECORDED ON REEL 012201, FRAME 0748.
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| 1-1, KAMIKODANAKA 4-CHOME, NAKAHARA-KU |
| KAWASAKI-SHI, KANAGAWA, 211-8588, JAPAN |
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| ARMSTRONG, WESTERMAN & HATTORI, LLP |
| MEL R. QUINTOS |
| 1725 K STREET, N.W. |
| SUITE 1000 |
| WASHINGTON, DC 20006 |
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