Patent Assignment Abstract of Title
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Total Assignments:
4
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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09987276
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Filing Dt:
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11/14/2001
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Publication #:
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Pub Dt:
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12/26/2002
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Inventors:
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Yu Yamamoto, Yoshio Inoue
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Title:
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METHOD OF DESIGNING LOGIC CIRCUIT, AND COMPUTER PRODUCT
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2-3, MARUNOUCHI 2-CHOME, CHIYODA-KU |
| TOKYO, JAPAN 100-8 |
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| LEYDIG, VOIT & MAYER, LTD. |
| JEFFREY A. WYAND |
| 700 THIRTEENTH ST., N.W., SUITE 300 |
| WASHINGTON, D.C. 20005-3960 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 4-1, MARUNOUCHI 2-CHOME, CHIYODA-KU |
| TOKYO, JAPAN 100-6334 |
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| MCDERMOTT, WILL & EMERY |
| STEPHEN A. BECKER |
| 600 13TH STREET, N.W. |
| WASHINGTON, DC 20005-3096 |
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Assignment:
3
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 4-1, MARUNOUCHI 2-CHOME, CHIYODA-KU |
| TOKYO, JAPAN 100-6334 |
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| MCDERMOTT, WILL & EMERY |
| STEPHEN A. BECKER |
| 600 13TH STREET, N.W. |
| WASHINGTON, DC 20005-3096 |
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Assignment:
4
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CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
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| 1753, SHIMONUMABE |
| NAKAHARA-KU |
| KAWASAKI-SHI, KANAGAWA, JAPAN |
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| JEFFREY A. WYAND |
| 700 THIRTEENTH STREET, N. W. |
| SUITE 300 |
| WASHINGTON, DC 20005 |
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