Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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10152007
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Filing Dt:
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05/22/2002
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Publication #:
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Pub Dt:
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06/26/2003
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Inventors:
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Yutaka Uneme, Hideaki Nagasawa
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT HAVING A GATE ARRAY STRUCTURE
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2-3, MARUNOUCHI 2-CHOME, CHIYODA-KU |
| TOKYO, JAPAN 100-8 |
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| LEYDIG, VOIT & MAYER, LTD. |
| JEFFREY A. WYAND |
| 700 THIRTEENTH STREET, N.W., SUITE 300 |
| WASHINGTON, D.C. 20005-3960 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 4-1, MARUNOUCHI 2-CHOME, CHIYODA-KU |
| TOKYO, JAPAN 100-6334 |
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| MCDERMOTT, WILL & EMERY |
| STEPHEN A. BECKER |
| 600 13TH STREET, N.W. |
| WASHINGTON, DC 20005-3096 |
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Assignment:
3
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 4-1, MARUNOUCHI 2-CHOME, CHIYODA-KU |
| TOKYO, JAPAN 100-6334 |
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| MCDERMOTT, WILL & EMERY |
| STEPHEN A. BECKER |
| 600 13TH STREET, N.W. |
| WASHINGTON, DC 20005-3096 |
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