Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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03/08/2005
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Application #:
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10359707
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Filing Dt:
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02/07/2003
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Publication #:
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Pub Dt:
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08/14/2003
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Inventors:
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Masahiko Tomizawa, Masahiko Nishiyama
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Title:
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Semiconductor integrated circuit device capable of switching mode for trimming internal circuitry through JTAG boundary scan method
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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6, KANDA SURUGADAI 4-CHOME |
CHIYODA-KU, TOKYO, JAPAN |
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JOSUIHONCHO 5-CHOME |
KODAIRA-SHI, TOKYO, JAPAN |
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REED SMITH LLP |
STANLEY P. FISHER |
3110 FAIRVIEW PARK DR. |
SUITE 1400 |
FALLS CHURCH, VA. 22042 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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1753 SHIMONUMABE, NAKAHARA-KU, KAWASAKI-SHI |
KANAGAWA 211-8668, JAPAN |
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ANTONELLI, TERRY, STOUT & KRAUS, LLP |
1300 N. 17TH ST., SUITE 1800 |
ARLINGTON, VA 22209 |
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