Patent Assignment Abstract of Title
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Total Assignments:
4
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Patent #:
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Issue Dt:
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05/22/2007
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Application #:
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10430319
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Filing Dt:
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05/07/2003
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Publication #:
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Pub Dt:
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12/04/2003
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Inventors:
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Yoshio Takazawa, Toshio Yamada, Kazumasa Yanagisawa, Takashi Hayasaka
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT AND TESTING METHOD THEREOF
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 6, KANDA SURUGADAI 4-CHOME CHIYODA-KU |
| TOKYO, JAPAN |
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| 22-1, JOSUIHONCHO 5-CHOME |
| KODAIRA-SHI, TOKYO, JAPAN |
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| REED SMTIH LLP |
| STANLEY P. FISHER |
| 3110 FAIRVIEW PARK DR. |
| SUITE 1400 |
| FALLS CHURCH, VA 22042 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 4-1, MARUNOUCHI 2-CHOME |
| CHIYODA-KU, TOKYO, JAPAN |
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| REED SMITH LLP |
| STANLEY P. FISHER |
| 3110 FAIRVIEW PARK DR., SUITE 1400 |
| FALLS CHURCH, VA 22042 |
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Assignment:
3
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MERGER (SEE DOCUMENT FOR DETAILS).
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| 1753 SHIMONUMABE, NAKAHARA-KU |
| KAWASAKI-SHI, KANAGAWA, JAPAN |
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| JUAN CARLOS A. MARQUEZ |
| STITES & HARBISON, PLLC |
| 1199 NORTH FAIRFAX STREET, SUITE 900 |
| ALEXANDRIA, VIRGINIA 22314 |
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Assignment:
4
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1753, SHIMONUMABE, NAKAHARA-KU, |
| KAWASAKI-SHI |
| KANAGAWA, JAPAN 211-8668 |
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| ANTONELLI, TERRY, STOUT, & KRAUS, LLP |
| 1300 NORTH 17TH STREET SUITE 1800 |
| ARLINGTON, VA 22209 |
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