Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10442107
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Filing Dt:
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05/21/2003
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Publication #:
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Pub Dt:
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12/04/2003
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Inventors:
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Toshihiro Ueda, Hiroshi Kikuchi
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Title:
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Logic simulation method for information handling system incorporated with memory macro
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1753 SHIMONUMABE, NAKAHARA-KU |
| KAWASAKI, KANAGAWA 211-8668, JAPAN |
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| FOLEY & LARDNER |
| DAVID A. BLUMENTHAL |
| WASHINGTON HARBOUR |
| 3000 K STREET, N.W., SUITE 500 |
| WASHINGTON, D.C. 20007-5143 |
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