Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10189870
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Filing Dt:
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07/03/2002
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Publication #:
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Pub Dt:
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01/08/2004
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Inventor:
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Rajesh Y. Pendurkar
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Title:
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Hierarchical test methodology for multi-core chips
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 4120 NETWORK CIRCLE |
| SANTA CLARA, CALIFORNIA 95054 |
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| WILLIAM L PARADICE III |
| 425 CALIFORNIA STREET, STE 900 |
| SAN FRANCISCO, CA 94104 |
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Assignment:
2
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SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
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| ELEVEN MADISON AVENUE |
| NEW YORK, NEW YORK 10010 |
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| JONATHAN SEIDEN, ESQ. |
| SKADDEN, ARPS, SLATE, MEAGHER |
| & FLOM LLP |
| FOUR TIMES SQUARE |
| NEW YORK, NEW YORK 10036 |
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Assignment:
3
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CORRECTION TO A PROPERTY NUMBER
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| ELEVEN MADISON AVENUE |
| NEW YORK, NEW YORK 10010 |
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| JONATHAN SEIDEN, ESQ. |
| SKADDEN, ARPS, SLATE, ET AL. |
| FOUR TIMES SQUARE |
| NEW YORK, NEW YORK 10036 |
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