Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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05/13/2008
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Application #:
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10226190
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Filing Dt:
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08/23/2002
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Publication #:
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Pub Dt:
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02/26/2004
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Inventors:
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Isao Takayanagi, Junichi Nakamura
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Title:
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CMOS APS WITH STACKED AVALANCHE MULTIPLICATION LAYER AND LOW VOLTAGE READOUT ELECTRONICS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 8000 S. FEDERAL WAY |
| BOISE, IDAHO 83707-0006 |
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| DICKSTEIN SHAPIRO MORIN ET AL. |
| THOMAS J. D'AMICO |
| 2101 L STREET NW |
| WASHINGTON, DC 20037-1526 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| C/O CITCO TRUSTEES (CAYMAN) LIMITED |
| REGATTA OFFICE PARK - WEST BAY ROAD |
| GRAND CAYMAN, CAYMAN ISLANDS Y1-1205 |
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| DICKSTEIN SHAPIRO LLP -THOMAS J. D'AMICO |
| 1825 EYE STREET N.W. |
| WASHINGTON, DC 20006 |
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