Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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09/05/2006
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Application #:
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10714393
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Filing Dt:
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11/17/2003
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Publication #:
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Pub Dt:
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07/15/2004
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Inventors:
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Hideyuki Noda, Kazutami Arimoto, Katsumi Dosaka, Takeshi Fujino
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING LOGIC CIRCUIT AND DYNAMIC RANDOM ACCESS MEMORY ON THE SAME CHIP
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 4-1, MARUNOUCHI 2-CHOME |
| CHIYODA-KU, TOKYO 100-6334, JAPAN |
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| MCDERMOTT WILL & EMERY LLP |
| 600 13TH STREET, NW |
| WASHINGTON, DC 20005-3096 |
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Assignment:
2
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CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
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| 1753, SHIMONUMABE, NAKAHARA-KU, KAWASAKI-SHI, |
| KANAGAWA, JAPAN |
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| MCDERMOTT WILL & EMERY LLP |
| 600 THIRTEENTH STREET, N.W. |
| WASHINGTON, DC 20005-3096 |
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Assignment:
3
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| 2-24, TOYOSU 3-CHOME, KOUTOU-KU |
| TOKYO, JAPAN |
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| MATTINGLY & MALUR, PC |
| 1800 DIAGONAL ROAD |
| SUITE 210 |
| ALEXANDRIA, VA 22314 |
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