Patent Assignment Abstract of Title
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Total Assignments:
4
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Patent #:
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Issue Dt:
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10/11/2005
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Application #:
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09997877
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Filing Dt:
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11/29/2001
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Publication #:
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Pub Dt:
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10/07/2004
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Inventors:
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William J. Earl, Jeff Tofano
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Title:
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FAULT TOLERANCE USING LOGICAL CHECKPOINTING IN COMPUTING SYSTEMS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 45700 NORTHPORT LOOP EAST |
| FREMONT, CALIFORNIA 94538 |
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| MORRISON & FOERSTER LLP |
| DOUGLAS G. HODDER |
| 755 PAGE MILL ROAD |
| PALO ALTO, CALIFORNIA 94304-1018 |
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Assignment:
2
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CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
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| 170 BAY TECH DRIVE |
| SAN JOSE, CALIFORNIA 95134 |
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| GRAY CARY WARE & FREIDENRICH LLP |
| ATTN: PATENT DEPARTMENT |
| DAVID L. ALBERTI |
| 2000 UNIVERSITY AVENUE |
| EAST PALO ALTO, CA 94303 |
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Assignment:
3
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| 400 HAMILTON AVENUE |
| SUITE 310 |
| PALO ALTO, CALIFORNIA 94301 |
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| EILEEN BAGARELLA |
| 934 CHURCH STREET C/O DESIGN CENTRIX |
| HERCULES TECHNOLOGY GROWTH CAPITAL, INC. |
| ELMHURST, IL 60126 |
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Assignment:
4
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| 20418 IRON SPRINGS RD |
| LOS GATOS, CALIFORNIA 95033 |
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| EILEEN M. BAGARELLA |
| C/O DESIGN CENTRIX, 934 CHURCH STREET |
| ELMHURST, IL 60126 |
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