Patent Assignment Abstract of Title
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Total Assignments:
1
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10729092
|
Filing Dt:
|
12/05/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/17/2005
| | | | |
|
Inventors:
|
Chun-Chieh Lin, Wen-Chin Lee, Yee-Chia Yeo, Chenming Hu
|
|
Title:
|
Structure and method of forming integrated circuits utilizing strained channel transistors
|
|
|
Assignment:
1
|
|
|
|
|
|
|
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
|
|
|
|
|
|
|
|
|
| NO. 6, LI-HSIN RD. 6 |
| SCIENCE-BASED INDUSTRIAL PARK |
| HSIN-CHU, TAIWAN 300-77 |
|
|
|
|
| SLATER & MATSIL, L.L.P. |
| STEVEN H. SLATER |
| 17950 PRESTON RD. |
| SUITE 1000 |
| DALLAS, TX 75252-5793 |
|
|
Search Results as of:
05/09/2024 12:47 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
