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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
Issue Dt:
06/27/2006
Application #:
10650010
Filing Dt:
08/27/2003
Publication #:
Pub Dt:
03/03/2005
Inventors:
Attila Kovacs, Jeffrey A. Buckles
Title:
SYSTEM AND METHOD FOR REDUCING TIMING VIOLATIONS DUE TO CROSSTALK IN AN INTEGRATED CIRCUIT DESIGN
Assignment: 1
Reel/Frame:
014940/0681Recorded: 02/02/2004Pages: 2
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
Exec Dt:
01/12/2004
Exec Dt:
01/12/2004
Assignee:
2880 SCOTT BOULEVARD
SANTA CLARA, CALIFORNIA 95050-2554
Correspondent:
CAMPBELL STEPHENSON ASCOLESE LLP
BRENNA A. BROCK
4807 SPICEWOOD SPRINGS ROAD
BUILDING 4, SUITE 201
AUSTIN, TEXAS 78759
Assignment: 2
Reel/Frame:
026110/0643Recorded: 03/31/2011Pages: 9
Conveyance:
MERGER (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
04/01/2010
Assignee:
2880 SCOTT BOULEVARD
SANTA CLARA, CALIFORNIA 95050-2554
Correspondent:
ERIC A. STEPHENSON
CAMPBELL STEPHENSON LLP
11401 CENTURY OAKS TERRACE
BUILDING H. SUITE 250
AUSTIN, TEXAS 78758

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