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Patent Assignment Abstract of Title

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Total Assignments: 1

Patent #:	7117291	Issue Dt:	10/03/2006	Application #:	10787240	Filing Dt:	02/27/2004
Publication #:	20050125594	Pub Dt:	06/09/2005
Inventors:	Hans Jurgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, Hiroshi Uchida, Zhaomin Zhu et al
Title:	MEMORY WITH SYNCHRONOUS BANK ARCHITECTURE

Assignment: 1

Reel/Frame:

Recorded: 02/27/2004

Pages: 3

Conveyance:

ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Assignors:

MATTAUSCH, HANS JURGEN

Exec Dt:

02/05/2004

KOIDE, TETSUSHI

Exec Dt:

02/05/2004

HIRONAKA, TETSUO

Exec Dt:

02/12/2004

UCHIDA, HIROSHI

Exec Dt:

02/17/2004

Exec Dt:

02/06/2004

Exec Dt:

02/06/2004

Assignee:

SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER

3-17-2, SHIN-YOKOHAMA KOHOKU-KU, YOKOHAMA-SHI

KANAGAWA 222-0033, JAPAN

Correspondent:

MCDERMOTT, WILL & EMERY

STEPHEN A. BECKER

600 13TH STREET, N.W.

WASHINGTON, D.C. 20005-3096

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