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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
Issue Dt:
08/14/2007
Application #:
10972361
Filing Dt:
10/26/2004
Publication #:
Pub Dt:
06/30/2005
Inventors:
Jyotirmoy Daw, Sanjay Gupta, Suresh Krishnamurthy
Title:
METHOD AND SYSTEM FOR HARDWARE ACCELERATED VERIFICATION OF DIGITAL CIRCUIT DESIGN AND ITS TESTBENCH
Assignment: 1
Reel/Frame:
016566/0825Recorded: 09/21/2005Pages: 4
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
08/26/2005
Assignee:
8005 SW BOECKMAN DRIVE
WILSONVILLE, OREGON 97070-7777
Correspondent:
BANNER & WITCOFF, LTD.
ELEVENTH FLOOR, 1001 G. STREET, N.W.
WASHINGTON, DC 20001-4597
Assignment: 2
Reel/Frame:
057279/0707Recorded: 06/16/2021Pages: 7
Conveyance:
MERGER AND CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Assignors:
Exec Dt:
12/30/2020
Newly Merged Entity Data
Exec Dt:
12/30/2020
Newly Merged Entity's New Name:
5800 GRANITE PARKWAY, SUITE 600
PLANO, TEXAS 75024
Correspondent:
SIEMENS CORPORATION IP DEPT - MAIL CODE INT-244
3850 QUADRANGLE BOULEVARD
ORLANDO, FL 32817

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