Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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04/24/2007
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Application #:
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10918513
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Filing Dt:
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08/13/2004
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Publication #:
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Pub Dt:
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07/14/2005
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Inventors:
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Harsanjeet Singh, Ankan Pramanick, Mark Elston, Yoshifumi Tahara, Toshiaki Adachi
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Title:
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METHOD AND STRUCTURE TO DEVELOP A TEST PROGRAM FOR SEMICONDUCTOR INTEGRATED CIRCUITS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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3201 SCOTT BOULEVARD |
SANTA CLARA, CALIFORNIA 95054 |
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MORRISON & FOERSTER LLP |
THOMAS CHAN |
755 PAGE MILL ROAD |
PALO ALTO, CA 94304 |
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Assignment:
2
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1-6-2, MARUNOUCHI, CHIYODA-KU |
TOKYO, JAPAN 100-0005 |
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ADVANTEST C/O MURABITO HAO & BARNES LLP |
TWO NORTH MARKET STREET |
THIRD FLOOR |
SAN JOSE, CA 95113 |
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