Patent Assignment Abstract of Title
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Total Assignments:
1
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10790205
|
Filing Dt:
|
03/02/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/08/2005
| | | | |
|
Inventors:
|
Jia-Pei Shen, Chien-Meen Hwang, Chih (Rex) Hsueh, Orlando Canelones
|
|
Title:
|
Fast fourier transform circuit having partitioned memory for minimal latency during in-place computation
|
|
|
Assignment:
1
|
|
|
|
|
|
|
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
|
|
|
|
|
|
|
|
|
| ONE AMD PLACE, P.O. BOX 3453 |
| SUNNYVALE, CALIFORNIA 94088-3453 |
|
|
|
|
| MANELLI DENISON & SELTER, P.L.L.C. |
| 2000 M STREET, N.W., 7TH FLOOR |
| WASHINGTON, D.C. 20036-3307 |
|
|
Search Results as of:
05/22/2024 05:26 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
