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Patent Assignment Abstract of Title
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Total Assignments: 3
Patent #:
NONE
Issue Dt:
Application #:
10854314
Filing Dt:
05/26/2004
Publication #:
Pub Dt:
12/01/2005
Inventor:
Perry H. Pelley
Title:
Cache line memory and method therefor
Assignment: 1
Reel/Frame:
015385/0738Recorded: 05/26/2004Pages: 3
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
05/25/2004
Assignee:
6501 WILLIAM CANNON DRIVE WEST
LAW DEPARTMENT
AUSTIN, TEXAS 78735
Correspondent:
FREESCALE SEMICONDUCTOR, INC.
MD: TX32/PLO2
7700 W. PARMER LANE
AUSTIN, TEXAS 78729
Assignment: 2
Reel/Frame:
018855/0129Recorded: 02/02/2007Pages: 450
Conveyance:
SECURITY AGREEMENT
Assignors:
Exec Dt:
12/01/2006
Exec Dt:
12/01/2006
Exec Dt:
12/01/2006
Exec Dt:
12/01/2006
Assignee:
390 GREENWICH STREET
NEW YORK, NEW YORK 10013
Correspondent:
CBCINNOVIS DBA FEDERAL RESEARCH
1023 FIFTEENTH STREET, NW, STE 401
ATTN: OLEH HERELIUK
WASHINGTON, DC 20005
Assignment: 3
Reel/Frame:
037354/0225Recorded: 12/21/2015Pages: 373
Conveyance:
PATENT RELEASE
Assignor:
Exec Dt:
12/07/2015
Assignee:
6501 WILLIAM CANNON DRIVE WEST
AUSTIN, TEXAS 78735
Correspondent:
IP RESEARCH PLUS, INC.
21 TADCASTER CIRCLE
ATTN: PENELOPE J.A. AGODOA
WALDORF, MD 20602

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