Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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03/20/2007
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Application #:
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11017730
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Filing Dt:
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12/22/2004
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Publication #:
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Pub Dt:
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02/16/2006
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Inventor:
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Hiroaki Iwashita
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Title:
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LOGIC VERIFICATION DEVICE, LOGIC VERIFICATION METHOD, AND COMPUTER PRODUCT
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1-1, KAMIKODANAKA 4-CHOME |
| NAKAHARA-KU, KAWASAKI-SHI |
| KANAGAWA 211-8588, JAPAN |
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| STAAS & HALSEY LLP |
| ATTENTION: H.J. STAAS |
| 1201 NEW YORK AVENUE, N.W. |
| SUITE 700 |
| WASHINGTON, DC 20005 |
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