Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10956656
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
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03/30/2006
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Inventors:
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Chok J. Chia, Wee Keong Liew, Seng Sooi Lim
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Title:
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Semiconductor package with wire bond arrangement to reduce cross talk for high speed circuits
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1621 BARBER LANE |
| MILPITAS, CALIFORNIA 95035 |
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| LSI LOGIC CORPORATION |
| JAMES W. ROSE |
| 1621 BARBER LANE |
| MS: D-106 |
| MILPITAS, CA 95035 |
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