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Patent Assignment Abstract of Title
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Total Assignments: 1
Patent #:
Issue Dt:
07/07/2009
Application #:
11330194
Filing Dt:
01/12/2006
Publication #:
Pub Dt:
07/20/2006
Inventors:
Hiroyasu Kunitomo, Tomoaki Nimura, Isamu Kuno, Ryuji Ariyoshi
Title:
SEMICONDUCTOR INTEGRATED CIRCUIT HAVING A REDUCED PARASITIC CAPACITANCE AND SHORT START-UP TIME
Assignment: 1
Reel/Frame:
017467/0835Recorded: 01/12/2006Pages: 4
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
Exec Dt:
01/04/2006
Exec Dt:
01/05/2006
Exec Dt:
01/05/2006
Exec Dt:
01/04/2006
Assignee:
MAKUHARI TECHNO GARDEN B5, 1-3, NAKASE, MIHAMA-KU
CHIBA 261-8501, JAPAN
Correspondent:
JAMES A. OLIFF
OLIFF & BERRIDGE, PLC
P.O. BOX 19928
ALEXANDRIA, VA 22320

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