Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10564473
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Filing Dt:
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01/13/2006
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Publication #:
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Pub Dt:
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07/27/2006
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Inventors:
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Masaki Murase, Yoshiharu Nakajima, Yoshitoshi Kida
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Title:
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Delay time correction circuit, video data processing circuit, and flat display device
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 7-35 KITASHINAGAWA 6-CHOME |
| SHINAGAWA-KU |
| TOKYO, JAPAN |
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| RONALD P. KANANEN |
| RADER, FISHMAN & GRAUER PLLC |
| 1233 20TH STREET, N.W. |
| SUITE 501 |
| WASHINGTON, DC 20036 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 50 AZA KAMIFUNAKI, O-AZA OGAWA |
| HIGASHIURA-CHO, CHITA-GUN, |
| AICHI-KEN, JAPAN 470-2102 |
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| RADER, FISHMAN & GRAUER PLLC |
| 1233 20TH STREET N.W., SUITE 501 |
| WASHINGTON, DC 20036 |
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