Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10588956
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Filing Dt:
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06/06/2007
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Publication #:
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Pub Dt:
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11/15/2007
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Inventor:
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Hiroshi Kawamoto
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Title:
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Integrated Circuit Design Meethod, Design Assistance Program and Integrated Circuit Design System Using Such Integrated Circuit Design Method
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1-8 HONCHO-4 CHOME, KAWAGUCHI-SHI |
| SAITAMA 332-0012, JAPAN |
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| RONALD P. KANANEN |
| RADER, FISHMAN & GRAUER PLLC |
| 1233 20TH STREET, N.W. |
| SUITE 501 |
| WASHINGTON, DC 20036 |
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