Patent Assignment Abstract of Title
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Total Assignments:
2
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12189408
|
Filing Dt:
|
08/11/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/19/2009
| | | | |
|
Inventors:
|
Shuuetsu KINOSHITA, Kenichi SHINDATE, Keitaro ISHIDA
|
|
Title:
|
METHOD OF DESIGNING A CIRCUIT FOR OPTIMIZING OUTPUT BIT LENGTH AND INTEGRATED CIRCUIT THEREFOR
|
|
|
Assignment:
1
|
|
|
|
|
|
|
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
|
|
|
|
|
|
|
|
|
| 7-12, TORANOMON, 1-CHOME, MINATO-KU |
| TOKYO, JAPAN 105-8460 |
|
|
|
|
| STUDEBAKER & BRACKETT PC |
| 1890 PRESTON WHITE DRIVE |
| SUITE 105 |
| RESTON, VA 20191 |
|
|
|
Assignment:
2
|
|
|
|
|
|
|
CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
|
|
|
|
|
|
|
|
|
| 550-1 HIGASHIASAKAWA-CHO |
| HACHIOJI-SHI, TOKYO, JAPAN 193-8550 |
|
|
|
|
| KUBOTERA & ASSOCIATES, LLC |
| 200 DAINGERFIELD ROAD, SUITE 202 |
| ALEXANDRIA, VA 22314 |
|
|
Search Results as of:
04/29/2024 07:08 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
