Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12457930
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Filing Dt:
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06/25/2009
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Publication #:
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Pub Dt:
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12/31/2009
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Inventors:
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Satoshi Nakamura, Tsutomu Hara, Yukitoshi Hirose, Ken Iwakura, Mitsuaki Katagiri et al
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Title:
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Semiconductor device or printed wiring board design method and design support system that implements settings by using a semiconductor device model that expresses parasitic elements that occur when packaged
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2-1, YAESU 2-CHOME, CHUO-KU |
| TOKYO, JAPAN |
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| SEAN M. MCGINN, ESQ. |
| MCGINN INTELLECTUAL PROPERTY LAW GROUP, |
| PLLC |
| 8321 OLD COURTHOUSE ROAD, SUITE 200 |
| VIENNA, VIRGINIA 22182-3817 |
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