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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
Issue Dt:
07/10/2012
Application #:
12651739
Filing Dt:
01/04/2010
Publication #:
Pub Dt:
07/08/2010
Inventor:
Taketoshi Tsurumoto
Title:
LAYOUT VERIFICATION DEVICE, LAYOUT VERIFICATION PROGRAM, AND LAYOUT VERIFICATION METHOD OF LAYOUT PATTERN OF SEMICONDUCTOR DEVICE
Assignment: 1
Reel/Frame:
023729/0318Recorded: 01/04/2010Pages: 2
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
12/04/2009
Assignee:
1753 SHIMONUMABE, NAKAHARA-KU
KAWASAKI, KANAGAWA, JAPAN 211-8668
Correspondent:
SUGHRUE MION, PLLC
2100 PENNSYLVANIA AVENUE, N.W.
SUITE 800
WASHINGTON, DC 20037-3213
Assignment: 2
Reel/Frame:
025193/0138Recorded: 10/26/2010Pages: 9
Conveyance:
CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
04/01/2010
Assignee:
1753 SHIMONUMABE, NAKAHARA-KU,
KAWASAKI-SHI, KANAGAWA, JAPAN 211-8668
Correspondent:
SUGHRUE MION, PLLC
2100 PENNSYLVANIA AVENUE, N.W.
SUITE 800
WASHINGTON, DC 20037

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