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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
8493116
Issue Dt:
07/23/2013
Application #:
13232555
Filing Dt:
09/14/2011
Publication #:
20120062294
Pub Dt:
03/15/2012
Inventors:
Jong-Ryun CHOI, Seong-Ook Jung, Suho Kim, Heechai Kang, Kyungho Ryu
Title:
CLOCK DELAY CIRCUIT AND DELAY LOCKED LOOP INCLUDING THE SAME
Assignment: 1
Reel/Frame:
027282/0367Recorded: 11/28/2011Pages: 8
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
CHOI, JONG-RYUN
Exec Dt:
10/25/2011
JUNG, SEONG-OOK
Exec Dt:
10/25/2011
KIM, SUHO
Exec Dt:
10/25/2011
KANG, HEECHAI
Exec Dt:
10/25/2011
RYU, KYUNGHO
Exec Dt:
10/25/2011
Assignee:
SAMSUNG ELECTRONICS CO., LTD.
416 MAETAN-DONG, YEONGTONG-GU
SUWON-SI
GYEONGGI-DO, KOREA, REPUBLIC OF
Correspondent:
MYERS BIGEL SIBLEY & SAJOVEC/KSC
PO BOX 37428
RALEIGH, NC 27627
Assignment: 2
Reel/Frame:
030653/0649Recorded: 06/20/2013Pages: 7
Conveyance:
NUNC PRO TUNC ASSIGNMENT (SEE DOCUMENT FOR DETAILS).
Assignors:
JUNG, SEONG-OOK
Exec Dt:
04/18/2013
RYU, KYUNGHO
Exec Dt:
04/18/2013
Assignee:
INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
50 YONSEI-RO, SEODAEMUN
SEOUL, KOREA, REPUBLIC OF 120-749
Correspondent:
GWEN R. BAILEY/MBSS
4140 PARKLAKE AVENUE, SUITE 600
RALEIGH, NC 27612

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