Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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05/13/2014
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Application #:
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13540520
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Filing Dt:
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07/02/2012
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Publication #:
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Pub Dt:
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10/24/2013
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Inventors:
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Sheng-Jhih Jiang, Tsung-Yi Ho, Chan-Liang Wu
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Title:
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FLOORPLANNING METHOD FOR AN ANALOG INTEGRATED CIRCUIT LAYOUT
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| NO.1, UNIVERSITY ROAD |
| TAINAN CITY, TAIWAN 701 |
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| NO.26, ZILIAN RD., XINSHI DIST. |
| TAINAN CITY, TAIWAN 74148 |
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| STOUT, UXA, BUYAN & MULLINS LLP |
| 4 VENTURE, SUITE 300 |
| IRVINE, CA 92618 |
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