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Patent Assignment Abstract of Title
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Total Assignments: 1
Patent #:
NONE
Issue Dt:
Application #:
14284570
Filing Dt:
05/22/2014
Publication #:
Pub Dt:
11/27/2014
Inventors:
Joseph M. RANISH, Satheesh KUPPURAO, Kailash Kiran PATALAY, Paul BRILLHART
Title:
COATED LINER ASSEMBLY FOR A SEMICONDUCTOR PROCESSING CHAMBER
Assignment: 1
Reel/Frame:
032948/0529Recorded: 05/22/2014Pages: 3
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
Exec Dt:
04/23/2014
Exec Dt:
04/11/2014
Exec Dt:
04/11/2014
Exec Dt:
04/16/2014
Assignee:
3050 BOWERS AVENUE
SANTA CLARA, CALIFORNIA 95054
Correspondent:
KEITH TABOADA
595 SHREWSBURY AVENUE
SUITE 100
SHREWSBURY, NJ 07702

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