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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
9537017
Issue Dt:
01/03/2017
Application #:
14608742
Filing Dt:
01/29/2015
Publication #:
20150179824
Pub Dt:
06/25/2015
Inventors:
Kevin Lu, Max Chen, Benson Wang, Warren Chiang
Title:
PROCESS FOR FORMING A PLANAR DIODE USING ONE MASK
Assignment: 1
Reel/Frame:
039698/0694Recorded: 09/12/2016Pages: 3
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
WANG, BENSON
Exec Dt:
10/03/2013
LU, KEVIN
Exec Dt:
10/01/2013
CHIANG, WARREN
Exec Dt:
10/03/2013
CHEN, MAX
Exec Dt:
10/03/2013
Assignee:
VISHAY GENERAL SEMICONDUCTOR LLC
150 MOTOR PARKWAY
HAUPPAUGE, NEW YORK 11788
Correspondent:
MAYER & WILLIAMS PC
928 MOUNTAIN AVENUE
MOUNTAINSIDE, NJ 07092
Assignment: 2
Reel/Frame:
049440/0876Recorded: 06/12/2019Pages: 79
Conveyance:
SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
VISHAY DALE ELECTRONICS, INC.
Exec Dt:
06/05/2019
DALE ELECTRONICS, INC.
Exec Dt:
06/05/2019
VISHAY DALE ELECTRONICS, LLC
Exec Dt:
06/05/2019
VISHAY-DALE, INC.
Exec Dt:
06/05/2019
VISHAY INTERTECHNOLOGY, INC.
Exec Dt:
06/05/2019
SILICONIX INCORPORATED
Exec Dt:
06/05/2019
VISHAY-SILICONIX, INC.
Exec Dt:
06/05/2019
VISHAY-SILICONIX
Exec Dt:
06/05/2019
VISHAY SPRAGUE, INC.
Exec Dt:
06/05/2019
VISHAY EFI, INC.
Exec Dt:
06/05/2019
SPRAGUE ELECTRIC COMPANY
Exec Dt:
06/05/2019
VISHAY GENERAL SEMICONDUCTOR, INC.
Exec Dt:
06/05/2019
Assignee:
JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
IL1-1145/54/63, P.O. BOX 6026
CHICAGO, ILLINOIS 60603-6026
Correspondent:
JAY DASILVA
1025 VERMONT AVE NW, SUITE 1130
COGENCY GLOBAL INC.
WASHINGTON, DC 20005

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