Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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01/19/2016
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Application #:
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14712864
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Filing Dt:
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05/14/2015
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Publication #:
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Pub Dt:
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11/19/2015
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Inventor:
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Cheng C. Wang
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Title:
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Clock Distribution Architecture for Logic Tiles of an Integrated Circuit and Method of Operation Thereof
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2570 W. EL CAMINO REAL, SUITE 210 |
| MOUNTAIN VIEW, CALIFORNIA 94040 |
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| NEIL A. STEINBERG |
| 5335 WISCONSIN AVE, NW SUITE 440 |
| WASHINGTON, D.C. 20015 |
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