Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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01/26/2016
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Application #:
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14320103
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Filing Dt:
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06/30/2014
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Publication #:
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Pub Dt:
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12/31/2015
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Inventors:
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Eiichi Fujikura, Susumu Okazaki, Takuya Futase, Fumiaki Toyama, Hiroaki Koketsu
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Title:
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NAND Flash Memory Integrated Circuits and Processes with Controlled Gate Height
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| TWO LEGACY TOWN CENTER, 6900 NORTH DALLAS PARKWAY |
| PLANO, TEXAS 75024 |
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| DAVIS WRIGHT TREMAINE LLP |
| 1201 THIRD AVENUE, SUITE 2200 |
| SEATTLE, WA 98101 |
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Assignment:
2
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CORRECTIVE ASSIGNMENT TO CORRECT THE INVENTOR EIICHI FUJIKAWA PREVIOUSLY RECORDED ON REEL 034120 FRAME 0820. ASSIGNOR(S) HEREBY CONFIRMS THE INVENTOR EIICHI FUJIKURA.
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| TWO LEGACY TOWN CENTER, 6900 NORTH DALLAS PARKWAY |
| PLANO, TEXAS 75024 |
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| DAVIS WRIGHT TREMAINE LLP |
| 1201 THIRD AVENUE, SUITE 2200 |
| SEATTLE, WA 98101 |
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Assignment:
3
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CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
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| 6900 DALLAS PARKWAY |
| SUITE 325 |
| PLANO, TEXAS 75024 |
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| SANDISK |
| 951 SANDISK DRIVE |
| PATENT DEPARTMENT/SIMONA BENJAMIN |
| MILPITAS, CA 95035 |
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