Patent Assignment Abstract of Title
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Total Assignments:
1
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2020
|
Application #:
|
15541434
|
Filing Dt:
|
07/03/2017
|
|
Publication #:
|
|
Pub Dt:
|
01/25/2018
| | | | |
|
Inventors:
|
Bin LUO, Hua WANG, Shouyin YE, Xuefei TANG, Jianbo LING, Jianming YE
|
|
Title:
|
CONFIGURATION AND TESTING METHOD AND SYSTEM FOR FPGA CHIP USING BUMPING PROCESS
|
|
|
Assignment:
1
|
|
|
|
|
|
|
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
|
|
|
|
|
|
|
|
|
| 2ND FLOOR, BUILDING 2, NO.351 GUOSHOUJING ROAD |
| PUDONG NEW AREA, SHANGHAI, CHINA 201203 |
|
|
|
|
| MAIER & MAIER, PLLC |
| 345 SOUTH PATRICK STREET |
| ALEXANDRIA, VA 22314 |
|
|
Search Results as of:
05/09/2024 05:10 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
