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Patent Assignment Abstract of Title
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Total Assignments: 1
Patent #:
10539613
Issue Dt:
01/21/2020
Application #:
15555076
Filing Dt:
09/01/2017
Publication #:
20180038909
Pub Dt:
02/08/2018
Inventors:
Yigang HE, Lifen YUAN, Yesheng SUN, Ying LONG, Zhijie YUAN, Lei WU, Chaolong ZHANG et al
Title:
ANALOG CIRCUIT FAULT DIAGNOSIS METHOD USING SINGLE TESTABLE NODE
Assignment: 1
Reel/Frame:
043527/0811Recorded: 09/07/2017Pages: 6
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
HE, YIGANG
Exec Dt:
07/12/2017
YUAN, LIFEN
Exec Dt:
07/12/2017
WU, LEI
Exec Dt:
07/12/2017
SUN, YESHENG
Exec Dt:
07/12/2017
ZHANG, CHAOLONG
Exec Dt:
07/12/2017
LONG, YING
Exec Dt:
07/12/2017
CHENG, ZHEN
Exec Dt:
07/12/2017
YUAN, ZHIJIE
Exec Dt:
07/12/2017
ZHAO, DEQIN
Exec Dt:
07/12/2017
Assignee:
HEFEI UNIVERSITY OF TECHNOLOGY
193 TUNXI ROAD, BAOHE DISTRICT HEFEI,
ANHUI, CHINA 230009
Correspondent:
JIANQ CHYUN INTELLECTUAL PROPERTY OFFICE
7F.-1, NO. 100, ROOSEVELT RD., SEC. 2,
TAIPEI, 100 TAIWAN

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