Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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05/18/2021
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Application #:
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15914553
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Filing Dt:
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03/07/2018
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Publication #:
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Pub Dt:
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07/12/2018
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Inventors:
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Duane CHAMPOUX, Mei-Mei SU
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Title:
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TEST ARCHITECTURE WITH AN FPGA BASED TEST BOARD TO SIMULATE A DUT OR END-POINT
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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1-32-1 ASAHI-CHO, 1 CHOME, NERIMA-KU |
TOKYO, JAPAN 179-0071 |
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ADVANTEST C/O MURABITO HAO & BARNES LLP |
TWO NORTH MARKET STREET |
THIRD FLOOR |
SAN JOSE, CA 95113 |
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Assignment:
2
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1-6-2, MARUNOUCHI, CHIYODA-KU |
TOKYO, JAPAN 100-0005 |
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ADVANTEST C/O MURABITO HAO & BARNES LLP |
TWO NORTH MARKET STREET |
THIRD FLOOR |
SAN JOSE, CA 95113 |
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