Patent Assignment Abstract of Title
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Total Assignments:
2
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2020
|
Application #:
|
16123123
|
Filing Dt:
|
09/06/2018
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2019
| | | | |
|
Inventors:
|
Masahiro KIYOOKA, Toshikatsu HIDA, Yoshihisa KOJIMA
|
|
Title:
|
MEMORY SYSTEM INCLUDING A MEMORY CONTROLLER AND ERROR CORRECTION CIRCUIT FOR READING MULTI-BIT DATA AND FOR DETECTING AND CORRECTING READ DATA ERRORS
|
|
|
Assignment:
1
|
|
|
|
|
|
|
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
|
|
|
|
|
|
|
|
|
| 1-1, SHIBAURA 1-CHOME, MINATO-KU |
| TOKYO, JAPAN 105-0023 |
|
|
|
|
| OBLON, ET AL. |
| 1940 DUKE STREET |
| ALEXANDRIA, VA 22314 |
|
|
|
Assignment:
2
|
|
|
|
|
|
|
CHANGE OF NAME AND ADDRESS
|
|
|
|
|
|
|
|
|
| 1-21, SHIBAURA 3-CHOME, MINATO-KU, |
| TOKYO, JAPAN |
|
|
|
|
| CPA GLOBAL LIMITED |
| LIBERATION HOUSE |
| CASTLE STREET |
| ST HELIER, JEI IBL JERSEY |
|
|
Search Results as of:
04/28/2024 08:43 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
