Patent Assignment Abstract of Title
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Total Assignments:
1
|
|
Patent #:
|
|
Issue Dt:
|
12/24/2019
|
Application #:
|
15991184
|
Filing Dt:
|
05/29/2018
|
|
Publication #:
|
|
Pub Dt:
|
12/05/2019
| | | | |
|
Inventors:
|
Chih-Han Lin, Kuei-Yu Kao, Shih-Yao Lin, Ming-Ching Chang, Chao-Cheng Chen et al
|
|
Title:
|
Methods of Manufacturing Transistor Gate Structures by Local Thinning of Dummy Gate Stacks using an Etch Barrier
|
|
|
Assignment:
1
|
|
|
|
|
|
|
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
|
|
|
|
|
|
|
|
|
| 8, LI-HSIN RD. 6 |
| HSINCHU SCIENCE PARK |
| HSINCHU, TAIWAN 300-78 |
|
|
|
|
| SLATER MATSIL, LLP/TSMC |
| 17950 PRESTON ROAD, SUITE 1000 |
| DALLAS, TX 75252 |
|
|
Search Results as of:
05/10/2024 11:32 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
