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Patent Assignment Abstract of Title
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Total Assignments: 1
Patent #:
NONE
Issue Dt:
Application #:
16583691
Filing Dt:
09/26/2019
Publication #:
20210098373
Pub Dt:
04/01/2021
Inventors:
Travis W. LAJOIE, Abhishek A. SHARMA, Juan G. ALZATE VINASCO, Chieh-Jen KU et al
Title:
INTEGRATED CIRCUIT STRUCTURES HAVING DIFFERENTIATED INTERCONNECT LINES IN A SAME DIELECTRIC LAYER
Assignment: 1
Reel/Frame:
051635/0420Recorded: 01/27/2020Pages: 8
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
LAJOIE, TRAVIS W.
Exec Dt:
11/05/2019
SHARMA, ABHISHEK A.
Exec Dt:
11/07/2019
ALZATE VINASCO, JUAN G.
Exec Dt:
11/04/2019
KU, CHIEH-JEN
Exec Dt:
11/04/2019
OGADHOH, SHEM O.
Exec Dt:
11/04/2019
GARDINER, ALLEN B.
Exec Dt:
11/04/2019
LIN, BLAKE C.
Exec Dt:
11/12/2019
WANG, YIH
Exec Dt:
12/18/2019
WANG, PEI-HUA
Exec Dt:
11/07/2019
KAVALIEROS, JACK T.
Exec Dt:
11/07/2019
SELL, BERNHARD
Exec Dt:
11/07/2019
GHANI, TAHIR
Exec Dt:
11/04/2019
Assignee:
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD
SANTA CLARA, CALIFORNIA 95054
Correspondent:
JUSTIN K. BRASK
1211 SW 5TH AVENUE, STE. 1600
PORTLAND, OR 97204

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