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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
Issue Dt:
11/28/2023
Application #:
17719974
Filing Dt:
04/13/2022
Publication #:
Pub Dt:
10/13/2022
Inventors:
Marcus van Ierssel, Prabhnoor Singh Kainth, Nanyan Wang
Title:
Methods and Circuits for Reducing Clock Jitter
Assignment: 1
Reel/Frame:
059609/0579Recorded: 04/15/2022Pages: 3
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
Exec Dt:
04/13/2021
Exec Dt:
04/15/2021
Exec Dt:
04/14/2021
Assignee:
4453 NORTH FIRST STREET, SUITE 100
SAN JOSE, CALIFORNIA 95134
Correspondent:
ANN WILLIAMS
4453 NORTH FIRST STREET, SUITE 100
SAN JOSE, CA 95134
Assignment: 2
Reel/Frame:
065017/0449Recorded: 09/22/2023Pages: 18
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
09/06/2023
Assignee:
2655 SEELY AVENUE
SAN JOSE, CALIFORNIA 95134
Correspondent:
HOLLAND & KNIGHT LLP
10 ST. JAMES AVENUE
BOSTON, MA 02116

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