Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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NONE
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Issue Dt:
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Application #:
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17737373
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Filing Dt:
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05/05/2022
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Publication #:
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Pub Dt:
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11/10/2022
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Inventors:
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Shan LU, Junmou ZHANG, Chuang ZHANG, Jian WANG, Yimin CHEN, Yuanlin CHENG
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Title:
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VOLTAGE DETECTION CIRCUIT AND METHOD FOR INTEGRATED CIRCUIT, AND INTEGRATED CIRCUIT
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 12655 WEST JEFFERSON BOULEVARD |
| SIXTH FLOOR, SUITE NO. 137 |
| LOS ANGELES, CALIFORNIA 90066 |
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| ROOM B-0035, 2/F, NO.3 BUILDING, NO.30 |
| SHIXING ROAD, SHIJINGSHAN DISTRICT |
| BEIJING, CHINA 100041 |
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| FAEGRE DRINKER BIDDLE & REATH LLP |
| 1500 K STREET, N.W. |
| SUITE 1100 |
| WASHINGTON, DC 20005 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| P.O. BOX 31119 GRAND PAVILION |
| HIBISCUS WAY, 802 WEST BAY ROAD |
| GRAND CAYMAN, CAYMAN ISLANDS KY1-1205 |
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| FAEGRE DRINKER BIDDLE & REATH LLP |
| 1500 K STREET, N.W. |
| SUITE 1100 |
| WASHINGTON, DC 20005-1209 |
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