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Patent Assignment Abstract of Title
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Total Assignments: 1
Patent #:
NONE
Issue Dt:
Application #:
17468319
Filing Dt:
09/07/2021
Publication #:
Pub Dt:
03/09/2023
Inventors:
Ali S. El-Zein, Viresh Paruthi, Alvan Wing Ng, Benedikt Geukes, Klaus-Dieter Schubert et al
Title:
LOGICAL CLOCK CONNECTION IN AN INTEGRATED CIRCUIT DESIGN
Assignment: 1
Reel/Frame:
057403/0514Recorded: 09/07/2021Pages: 6
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
Exec Dt:
09/07/2021
Exec Dt:
09/07/2021
Exec Dt:
09/07/2021
Exec Dt:
09/07/2021
Exec Dt:
09/07/2021
Exec Dt:
09/07/2021
Exec Dt:
09/07/2021
Exec Dt:
09/07/2021
Exec Dt:
09/07/2021
Exec Dt:
09/07/2021
Exec Dt:
09/07/2021
Exec Dt:
09/07/2021
Assignee:
NEW ORCHARD ROAD
ARMONK, NEW YORK 10504
Correspondent:
RUSSELL NG PLLC
8729 SHOAL CREEK BLVD., SUITE 100
AUSTIN, TX 78757

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