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Patent Assignment Abstract of Title
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Total Assignments: 1
Patent #:
NONE
Issue Dt:
Application #:
18305536
Filing Dt:
04/24/2023
Publication #:
Pub Dt:
08/17/2023
Inventors:
Jing-Huei Huang, Ya-Wen Chiu, Lun-Kuang Tan
Title:
Method for Reducing Line-End Space in Integrated Circuit Patterning
Assignment: 1
Reel/Frame:
063448/0915Recorded: 04/24/2023Pages: 3
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
Exec Dt:
05/05/2020
Exec Dt:
05/05/2020
Exec Dt:
05/05/2020
Assignee:
8, LI-HSIN RD. 6
HSINCHU SCIENCE PARK
HSINCHU, TAIWAN 300-78
Correspondent:
HAYNES AND BOONE, LLP
2323 VICTORY AVENUE
SUITE 700
DALLAS, TX 75219

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