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Patent Assignment Abstract of Title
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Total Assignments: 1
Patent #:
Issue Dt:
01/02/2024
Application #:
17742363
Filing Dt:
05/11/2022
Publication #:
Pub Dt:
11/16/2023
Inventors:
Albert Shih-Huai LIN, Niravkumar PATEL, Amitava MAJUMDAR, Jane Wang SOWARDS
Title:
INTEGRATED CIRCUIT CHIP TESTING INTERFACE WITH REDUCED SIGNAL WIRES
Assignment: 1
Reel/Frame:
059946/0067Recorded: 05/18/2022Pages: 6
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
Exec Dt:
04/29/2022
Exec Dt:
05/10/2022
Exec Dt:
05/12/2022
Exec Dt:
05/06/2022
Assignee:
2100 LOGIC DRIVE
SAN JOSE, CALIFORNIA 95124
Correspondent:
XILINX, INC.
2100 LOGIC DRIVE
SAN JOSE, CA 95124

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