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Patent Assignment Abstract of Title
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Total Assignments: 1
Patent #:
NONE
Issue Dt:
Application #:
18151556
Filing Dt:
01/09/2023
Publication #:
20240055371
Pub Dt:
02/15/2024
Inventors:
Der-Chyang Yeh, Kuo-Chiang Ting, Yu-Hsiung Wang, Chao-Wen Shih, Sung-Feng Yeh et al
Title:
INTEGRATED CIRCUIT PACKAGES AND METHODS OF FORMING THE SAME
Assignment: 1
Reel/Frame:
062316/0458Recorded: 01/09/2023Pages: 5
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
YEH, DER-CHYANG
Exec Dt:
10/31/2022
TING, KUO-CHIANG
Exec Dt:
10/27/2022
WANG, YU-HSIUNG
Exec Dt:
11/10/2022
SHIH, CHAO-WEN
Exec Dt:
11/03/2022
YEH, SUNG-FENG
Exec Dt:
10/27/2022
SUNG, TA HAO
Exec Dt:
10/27/2022
HUANG, CHENG-WEI
Exec Dt:
10/28/2022
WANG, YEN-PING
Exec Dt:
10/28/2022
HUANG, CHANG-WEN
Exec Dt:
10/28/2022
LIN, SHENG-TA
Exec Dt:
11/03/2022
HU, LI-CHENG
Exec Dt:
10/27/2022
WU, GAO-LONG
Exec Dt:
10/28/2022
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
8, LI-HSIN RD. 6, HSINCHU SCIENCE PARK
HSINCHU, TAIWAN 300-78
Correspondent:
SLATER MATSIL, LLP - TSMC
17950 PRESTON ROAD, SUITE 1000
DALLAS, TX 75252

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