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Total properties:
22
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Patent #:
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Issue Dt:
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05/29/1984
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Application #:
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06303374
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Filing Dt:
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09/18/1981
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Title:
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METHOD AND DEVICE FOR ENCODING PRODUCT AND PROGRAMMING INFORMATION IN SEMICONDUCTORS
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Patent #:
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Issue Dt:
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01/01/1985
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Application #:
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06343845
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Filing Dt:
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01/29/1982
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Title:
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METHOD OF FABRICATING AN MOS MEMORY ARRAY HAVING ELECTRICALLY- PROGRAMMABLE AND ELECTRICALLY-ERASABLE STORAGE DEVICES INCORPORATED THEREIN
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Patent #:
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Issue Dt:
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12/10/1985
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Application #:
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06343847
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Filing Dt:
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01/29/1982
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Title:
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ELECTRICALLY-PROGRAMMABLE AND ELECTRICALLY-ERASABLE MOS MEMORY DEVICE
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Patent #:
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Issue Dt:
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12/06/1983
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Application #:
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06346162
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Filing Dt:
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02/05/1982
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Title:
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METHOD AND DEVICE FOR PROVIDING PROCESS AND TEST INFORMATION IN SEMICONDUCTORS
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Patent #:
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Issue Dt:
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04/16/1985
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Application #:
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06346891
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Filing Dt:
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02/08/1982
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Title:
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CHARGE PUMP FOR PROVIDING PROGRAMMING VOLTAGE TO THE WORD LINES IN A SEMICONDUCTOR MEMORY ARRAY
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Patent #:
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Issue Dt:
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08/27/1985
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Application #:
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06367331
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Filing Dt:
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04/12/1982
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Title:
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ENABLING CIRCUIT FOR REDUNDANT WORD LINES IN A SEMICONDUCTOR MEMORY ARRAY
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Patent #:
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Issue Dt:
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12/18/1984
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Application #:
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06367332
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Filing Dt:
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04/12/1982
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Title:
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ELECTRICAL PARTITIONING SCHEME FOR IMPROVING YIELDS DURING THE MANUFACTURE OF SEMICONDUCTOR MEMORY ARRAYS
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Patent #:
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Issue Dt:
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08/13/1985
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Application #:
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06389819
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Filing Dt:
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06/18/1982
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Title:
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SENSE AMPLIFIER FOR USE WITH A SEMICONDUCTOR MEMORY ARRAY
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Patent #:
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Issue Dt:
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10/08/1985
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Application #:
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06439602
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Filing Dt:
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11/05/1982
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Title:
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NON-VOLATILE MEMORY CELL FUSE ELEMENT
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Patent #:
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Issue Dt:
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08/30/1988
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Application #:
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06546593
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Filing Dt:
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10/28/1983
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Title:
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FAULT-TOLERANT MEMORY ARRAY
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Patent #:
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Issue Dt:
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02/16/1988
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Application #:
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06581684
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Filing Dt:
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02/21/1984
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Title:
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CMOS EPROM SENSE AMPLIFIER
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Patent #:
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Issue Dt:
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09/16/1986
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Application #:
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06581685
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Filing Dt:
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02/21/1984
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Title:
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ERROR CHECKING AND CORRECTION CIRCUITRY FOR USE WITH AN ELECTRICALLY-PROGRAMMABLE AND ELECTRICALLY-ERASABLE MEMORY ARRAY
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Patent #:
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Issue Dt:
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10/14/1986
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Application #:
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06582438
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Filing Dt:
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02/22/1984
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Title:
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REDUNDANCY CIRCUIT FOR USE IN A SEMICONDUCTOR MEMORY ARRAY
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Patent #:
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Issue Dt:
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06/16/1987
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Application #:
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06699551
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Filing Dt:
|
02/08/1985
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Title:
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CHARGE PUMP FOR PROVIDING PROGRAMMING VOLTAGE TO THE WORD LINES IN A SEMICONDUCTOR MEMORY ARRAY
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|
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Patent #:
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|
Issue Dt:
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11/15/1988
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Application #:
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06868114
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Filing Dt:
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05/27/1986
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Title:
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APPARATUS FOR PAGE MODE PROGRAMMING OF AN EEPROM CELL ARRAY WITH FALSE LOADING PROTECTION
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Patent #:
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Issue Dt:
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11/08/1988
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Application #:
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06869207
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Filing Dt:
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05/30/1986
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Title:
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BLOCK ELECTRICALLY ERASABLE EEPROM
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Patent #:
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Issue Dt:
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10/20/1987
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Application #:
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06936965
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Filing Dt:
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12/01/1986
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Title:
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MOS FLOATING GATE MEMORY CELL AND PROCESS FOR FABRICATING SAME
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Patent #:
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Issue Dt:
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04/18/1989
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Application #:
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07074085
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Filing Dt:
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07/16/1987
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Title:
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MOS FLOATING GATE MEMORY CELL CONTAINING TUNNELING DIFFUSION REGION IN CONTACT WITH DRAIN AND EXTENDING UNDER EDGES OF FIELD OXIDE
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Patent #:
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Issue Dt:
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08/08/1989
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Application #:
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07179527
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Filing Dt:
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04/08/1988
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Title:
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THREE TRANSISTOR HIGH ENDURANCE EEPROM CELL
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Patent #:
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Issue Dt:
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12/19/1989
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Application #:
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07212974
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Filing Dt:
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06/29/1988
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Title:
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CURRENT-REGULATED, VOLTAGE-REGULATED ERASE CIRCUIT FOR EEPROM MEMORY CELLS
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|
|
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Patent #:
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|
Issue Dt:
|
07/02/1991
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Application #:
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07212975
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Filing Dt:
|
06/29/1988
|
|
Title:
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FAULT TOLERANT DIFFERENTIAL MEMORY CELL AND SENSING
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Patent #:
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|
Issue Dt:
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03/31/1992
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Application #:
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07551642
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Filing Dt:
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07/10/1990
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|
Title:
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APPARATUS FOR PAGE MODE PROGRAMMING OF AN EEPROM CELL ARRAY WITH FALSE LOADING PROTECTION
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