skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:006959/0230   Pages: 2
Recorded: 02/14/1994
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
03/19/1996
Application #:
08194988
Filing Dt:
02/14/1994
Title:
SEMICONDUCTOR INTEGRATED CIRCUIT WITH PROTECTION CIRCUIT AGAINST ELECTROSTATIC BREAKDOWN AND LAYOUT DESIGN METHOD THEREFOR
Assignors
1
Exec Dt:
02/09/1994
2
Exec Dt:
02/09/1994
3
Exec Dt:
02/09/1994
4
Exec Dt:
02/09/1994
5
Exec Dt:
02/09/1994
6
Exec Dt:
02/09/1994
Assignee
1
1015, KAMIKODANAKA, NAKAHARA-KU, KAWASAKI-SHI
KANAGAWA 211, JAPAN
Correspondence name and address
JAMES D. HALSEY, JR.
STAAS & HALSEY
1825 K STREET, N.W., SUITE 816
WASHINGTON, DC 20006

Search Results as of: 03/28/2024 06:29 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT