Patent Assignment Details
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Reel/Frame: | 006959/0230 | |
| Pages: | 2 |
| | Recorded: | 02/14/1994 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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03/19/1996
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Application #:
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08194988
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Filing Dt:
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02/14/1994
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT WITH PROTECTION CIRCUIT AGAINST ELECTROSTATIC BREAKDOWN AND LAYOUT DESIGN METHOD THEREFOR
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Assignee
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1015, KAMIKODANAKA, NAKAHARA-KU, KAWASAKI-SHI |
KANAGAWA 211, JAPAN |
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Correspondence name and address
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JAMES D. HALSEY, JR.
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STAAS & HALSEY
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1825 K STREET, N.W., SUITE 816
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WASHINGTON, DC 20006
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