Patent Assignment Details
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Reel/Frame: | 007743/0115 | |
| Pages: | 4 |
| | Recorded: | 10/12/1995 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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04/21/1998
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Application #:
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08541213
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Filing Dt:
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10/12/1995
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Title:
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PRINTED CIRCUIT BOARD LAYOUT TO MINIMIZE THE CLOCK DELAY CAUSED BY MISMATCH IN LENGTH OF METAL LINES AND ENHANCE THE THERMAL PERFORMANCE OF MICROELECTRONICS PACKAGES VIA CONDUCTION THROUGH THE PACKAGE LEADS
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Assignee
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LEGAL DEPARTMENT, MS/45 |
1109 MCKAY DRIVE |
SAN JOSE, CALIFORNIA 95131 |
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Correspondence name and address
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VLSI TECHNOLOGY, INC.
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WILLIAM G. BECKER, ESQ.
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1109 MCKAY DRIVE
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LEGAL DEPARTMENT, M/S 45
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SAN JOSE, CA 95131
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