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Total properties:
15
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Patent #:
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Issue Dt:
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09/03/1996
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Application #:
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07972149
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Filing Dt:
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11/05/1992
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Title:
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ELIMINATING RETIMING BOTTLENECKS TO IMPROVE PERFORMANCE OF SYNCHRONOUS SEQUENTIAL VLSI CIRCUITS
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Patent #:
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Issue Dt:
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04/30/1996
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Application #:
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08113056
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Filing Dt:
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08/25/1993
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Title:
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HIGH LEVEL SYNTHESIS FOR PARTIAL SCAN TESTING
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Patent #:
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Issue Dt:
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05/28/1996
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Application #:
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08127681
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Filing Dt:
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09/27/1993
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Title:
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METHOD OF FINDING MINIMUM-COST FEEDBACK-VERTEX SETS FOR A GRAPH FOR PARTIAL SCAN TESTING WITHOUT EXHAUSTIVE CYCLE ENUMERATION
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Patent #:
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Issue Dt:
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02/20/1996
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Application #:
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08144802
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Filing Dt:
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10/28/1993
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Title:
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INITIALIZABLE ASYNCHRONOUS CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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03/26/1996
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Application #:
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08148637
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Filing Dt:
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11/05/1993
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Title:
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BEHAVIORAL SYNTHESIS FOR RECONFIGURABLE DATAPATH STRUCTURES
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Patent #:
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Issue Dt:
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03/26/1996
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Application #:
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08161140
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Filing Dt:
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12/02/1993
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Title:
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SELECTION OF PARTIAL SCAN FLIP-FLOPS TO BREAK FEEDBACK CYCLES
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Patent #:
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Issue Dt:
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03/26/1996
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Application #:
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08161221
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Filing Dt:
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12/01/1993
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Title:
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RESYNTHESIS AND RETIMING FOR OPTIMUM PARTIAL SCAN TESTING
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Patent #:
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Issue Dt:
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06/25/1996
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Application #:
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08167337
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Filing Dt:
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12/15/1993
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Title:
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UPC-BASED TRAFFIC CONTROL FRAMEWORK FOR ATM NETWORKS
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Patent #:
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Issue Dt:
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04/09/1996
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Application #:
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08210122
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Filing Dt:
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03/17/1994
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Title:
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TESTING VLSI CIRCUITS FOR DEFECTS
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Patent #:
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Issue Dt:
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08/27/1996
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Application #:
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08254147
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Filing Dt:
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06/03/1994
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Title:
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HIGH LEVEL CIRCUIT DESIGN SYNTHESIS USING TRANSFORMATIONS
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Patent #:
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Issue Dt:
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03/26/1996
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Application #:
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08258585
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Filing Dt:
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06/10/1994
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Title:
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PARTIAL SCAN TESTABILITY UTILIZING RECONVERGENCE THROUGH SEQUENTIAL ELEMENTS
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Patent #:
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Issue Dt:
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04/30/1996
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Application #:
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08268823
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Filing Dt:
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06/30/1994
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Title:
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NON-SCAN DESIGN-FOR-TESTABILITY OF RT-LEVEL DATA PATHS
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Patent #:
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Issue Dt:
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03/12/1996
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Application #:
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08332978
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Filing Dt:
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11/01/1994
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Title:
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TEMPORAL PLACEMENT CONTROL OF VIDEO FRAMES IN B-ISDN NETWORKS
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Patent #:
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Issue Dt:
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09/10/1996
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Application #:
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08365971
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Filing Dt:
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12/27/1994
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Title:
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OPTIMAL RETIMING OF SYNCHRONOUS LOGIC CIRCUITS
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Patent #:
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Issue Dt:
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11/12/1996
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Application #:
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08539392
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Filing Dt:
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10/05/1995
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Title:
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TEST GENERATION OF SEQUENTIAL CIRCUITS USING SOFTWARE TRANSFORMATIONS
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