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Patent Assignment Details
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Reel/Frame:008620/0067   Pages: 2
Recorded: 06/13/1997
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
10/23/2001
Application #:
08874506
Filing Dt:
06/13/1997
Title:
METHOD AND APPARATUS FOR CIRCUIT DESIGNING OF AN LSI CIRCUIT WITHOUT ERROR PATHS
Assignors
1
Exec Dt:
04/18/1997
2
Exec Dt:
04/18/1997
3
Exec Dt:
04/18/1997
Assignee
1
1-1, KAMIKODANAKA 4-CHOME, NAKAHARA
KAWASAKI-SHI, KANAGAWA 211, JAPAN
Correspondence name and address
STAAS & HALSEY
JAMES D. HALSEY, JR.
700 ELEVENTH STREET, N.W.
SUITE 500
WASHINGTON, D.C. 20001

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