Patent Assignment Details
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| Reel/Frame: | 009099/0596 | |
| Pages: | 5 |
| | Recorded: | 04/13/1998 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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10/03/2000
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Application #:
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08996049
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Filing Dt:
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12/22/1997
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Title:
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DUAL PORT SRAM MEMORY FOR RUN TIME USE IN FPGA INTEGRATED CIRCUITS
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Assignee
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| P.O. BOX 3755 |
| 920 DE GUIGNE DRIVE |
| SUNNYVALE, CALIFORNIA 94088 |
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Correspondence name and address
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FLIESLER, DUBB, MEYER & LOVEJOY
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MARTIN C. FLIESLER, ESQ.
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FOUR EMBARCADERO CENTER, SUITE 400
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SAN FRANCISCO, CA 94111
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