Patent Assignment Details
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Reel/Frame: | 009112/0726 | |
| Pages: | 2 |
| | Recorded: | 04/21/1998 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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09/14/1999
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Application #:
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09063439
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Filing Dt:
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04/21/1998
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT ACHIEVING RELIABLE DATA LATCHING
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Assignee
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1-1, KAMIKODANAKA 4-CHOME, NAKAHARA-KU, KAWASAKI-SHI |
KANAGAWA, 211-8588, JAPAN |
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Correspondence name and address
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NIKAIDO, MARMELSTEIN, MURRAY & ORAM LLP
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CHARLES MARMELSTEIN
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METROPOLITAN SQUARE, 655 15TH STREET, NW
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SUITE 330 - G STREET LOBBY
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WASHINGTON, DC 20005-5701
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